发明名称 |
CLOCK/DATA REPRODUCTION UNIT, METHOD FOR CONTROLLING POWER THEREOF, AND PON SYSTEM |
摘要 |
<p>The purpose of the present invention is to reduce unnecessary power consumption when a clock/data reproduction unit in a terminal device of a PON system is booted from a power-saving state, and to make it possible to perform communication in a speedy and reliable manner. The clock/data reproduction unit is provided with a phase-locked loop for extracting a clock signal and a data signal from an input signal, the phase-locked loop being able to be set to normal mode or power-saving mode and including a voltage-controlled oscillator. The clock/data reproduction unit is further provided with a reference clock multiplication circuit for multiplying and outputting a reference clock signal, and with a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplication circuit before the phase-locked loop shifts from the power-saving mode to the normal mode.</p> |
申请公布号 |
WO2012117890(A1) |
申请公布日期 |
2012.09.07 |
申请号 |
WO2012JP54094 |
申请日期 |
2012.02.21 |
申请人 |
SUMITOMO ELECTRIC INDUSTRIES, LTD.;TANAKA, NARUTO |
发明人 |
TANAKA, NARUTO |
分类号 |
H04L7/033 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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