| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a wafer level package, a chip size package device, and a method of manufacturing a wafer level package capable of avoiding generation of cracks of a sealing frame at dicing, and suppressing generation of peeling in a wafer even through high-temperature processing after wet processing and liquid cleaning. <P>SOLUTION: There are provided a base wafer 22 on which a plurality of semiconductor chips 1 are mounted or formed in a plane, and a cover part wafer 23 opposed to the base wafer 22. The base wafer 22 and the cover part wafer 23 are bonded with interposing a frame-shaped sealing frame 4 sealing the periphery of the respective semiconductor chips 1 therebetween. A clearance 24 is formed between the sealing frames 4 in the respective semiconductor chips 1 adjacent to each other. A partial-coupling part 26 partially coupling both sealing frames 4 with each other is provided to the clearance 24 between the sealing frames 4 of the respective semiconductor chips 1 adjacent to each other. <P>COPYRIGHT: (C)2012,JPO&INPIT |
