发明名称 OUTPUT BUFFER CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To reduce a change in current consumption while holding a duty of an output signal. <P>SOLUTION: An output buffer circuit includes an output circuit (300), a first input circuit (210), a second input circuit (220), a first clamp circuit (110) and a second clamp circuit (120). The output circuit (300) includes a first output transistor (P301) and a second output transistor (N301), and outputs an output signal (VOUT). The first clamp circuit (110) and the second clamp circuit (120) each include a first conductivity type transistor (P111/P121) and a second conductivity type transistor (N111/N121) cascode-connected. The first clamp circuit (110) clamps an output voltage (VA1) of the first input circuit (210) for a predetermined period. The second clamp circuit (120) clamps an output voltage (VA2) of the second input circuit (220) for the predetermined period. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012169937(A) 申请公布日期 2012.09.06
申请号 JP20110030254 申请日期 2011.02.15
申请人 RENESAS ELECTRONICS CORP 发明人 TAKO TOSHIJI;TANGODEN ATSUSHI
分类号 H03K19/0175;H03K17/687 主分类号 H03K19/0175
代理机构 代理人
主权项
地址