| 摘要 |
<p>A memory controller delays accesses to a memory to ensure that the average time between accesses is above a threshold. Low priority accesses are delayed by a longer time than high priority accesses. The priority of the accesses may be related to the latency requirements of the access, the type of access or the source of the access. The accesses may be grouped into a number of priority categories, each category having a different access delay. The highest priority accesses may be delayed by the minimum access delay allowed by the circuit. If the average access delay falls below the threshold, the access delay of one of the categories of request may be increased. A maximum threshold for the average delay and a maximum delay for an access may also be used. The thresholds may be changed based on the temperature or power state of the circuit.</p> |
