| 摘要 |
A non-volatile memory structure (50, 60) is disclosed. LDD regions (72, 73) may be optionally formed through an ion implantation using a mask (61, 71) for protection of a gate channel region of an active area (56, 66). Two gates (52, 62, 53, 63) are apart from each other and disposed on an isolation structure (54) on two sides of a middle region of the active area (56, 66), respectively. The two gates (52, 62, 53, 63) may be each entirely disposed on the isolation structure (54) or partially to overlap a side portion of the middle region of the active area (56, 66). A charge-trapping layer (58) and a dielectric layer (69) are formed between the two gates (52, 62, 53, 63) and on the active area (56, 66) to serve as a storage node function. They may be further formed onto all sidewalls of the two gates (52, 62, 53, 63) to serve as spacers. Source/drain regions (78, 79) are formed through ion implantation using a mask (76, 82) for protection of the gates (52, 62, 53, 63) and the charge-trapping layer (58).
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