发明名称 |
Semiconductor device |
摘要 |
The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells. |
申请公布号 |
US8259524(B2) |
申请公布日期 |
2012.09.04 |
申请号 |
US20100838466 |
申请日期 |
2010.07.18 |
申请人 |
FUNANE KIYOTADA;YANAGITANI YUTA;TANAKA SHINJI;RENESAS ELECTRONICS CORPORATION |
发明人 |
FUNANE KIYOTADA;YANAGITANI YUTA;TANAKA SHINJI |
分类号 |
G11C7/10;G11C7/02;G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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