Apparatus and method for frequency synthesis using delay locked loop

摘要

An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch. If phases of a reference frequency signal and a feedback signal are the same and thus are locked, the DLL delays the reference frequency signal. The edge pulse generator generates a plurality of pulse signals representing phase delay amounts of signals. The LC tank switch combines the plurality of pulse signals and generates frequency.