发明名称 |
Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction |
摘要 |
A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
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申请公布号 |
US8258551(B2) |
申请公布日期 |
2012.09.04 |
申请号 |
US20090572228 |
申请日期 |
2009.10.01 |
申请人 |
BECKER SCOTT T.;SMAYLING MICHAEL C.;TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
H01L27/10 |
主分类号 |
H01L27/10 |
代理机构 |
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主权项 |
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地址 |
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