发明名称 |
Clock auto-phasing for reduced jitter |
摘要 |
The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal. |
申请公布号 |
US8258845(B1) |
申请公布日期 |
2012.09.04 |
申请号 |
US20050134117 |
申请日期 |
2005.05.20 |
申请人 |
ALEXANDER MARK A.;KOONTZ SEAN A.;XILINX, INC. |
发明人 |
ALEXANDER MARK A.;KOONTZ SEAN A. |
分类号 |
H03K3/00 |
主分类号 |
H03K3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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