| 摘要 |
A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal. |
