| 摘要 |
A fractional divider has been provided that allows for division ratios of 1:1 to 1:2N-1 with fine fractional resolution. To accomplish this, a phase blender (which is under the control of a state machine) is used to “blend” or interpolate consecutive phases of a clock signal from a delay locked loop to achieve a low deterministic jitter, while a sigma delta modulator can also be used to maintain low deterministic jitter while achieving the desired frequency resolution. |
