| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring structure capable of reducing the number of layers and substrate area at the same time with keeping properties within specifications. <P>SOLUTION: A plurality of wiring layers include a four-layered wiring part in which a power supply layer L4, a ground layer L3, a first signal wiring layer L2 and a second signal wiring layer L1 are sequentially arranged via an insulation layer in each interlayer from one side to another side in a lamination direction. The first and the second signal wiring layers L2, L1 include data signal (DQ) wiring in one layer and clock signal (CLK) wiring in the other layer, and those are arranged so as not to overlap with each other when viewed from the lamination direction at locations at least where the both wiring parts are parallel. <P>COPYRIGHT: (C)2012,JPO&INPIT |
