发明名称 PARALLEL FLIP-FLOP SETUP AND HOLD TIMING ANALYSIS
摘要 A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing. If the search window is not less than the predetermined window width, the system repeats the above, starting with dividing the new search window into four sections using three quadsection values.
申请公布号 US2012221313(A1) 申请公布日期 2012.08.30
申请号 US201113033961 申请日期 2011.02.24
申请人 PATRA KAUSHIK;ORACLE INTERNATIONAL CORPORATION 发明人 PATRA KAUSHIK
分类号 G06F17/50 主分类号 G06F17/50
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