发明名称 SNR IMPROVEMENT CIRCUIT, SYNCHRONIZATION INFORMATION DETECTION CIRCUIT, COMMUNICATION DEVICE, SNR IMPROVEMENT METHOD, AND SYNCHRONIZATION INFORMATION DETECTION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a technology that makes it possible to improve a packet catch rate, for example, in the case of being applied to a communication device. <P>SOLUTION: An SNR improvement circuit 4 improving an SNR of an input signal includes: a delay part 50 generating one or more delay signals by delaying the input signal; and an addition part 60 adding the one or more delay signals and the input signal before being delayed. The input signal includes periodic signals generated by repeating the same signal predetermined times at a predetermined cycle. The delay part 50 generates the one or more delay signals by using delay time that is an &alpha;-fold time of the predetermined cycle, where &alpha; is a natural number and is set at a value differing from each other for two or more delayed signals. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012165320(A) 申请公布日期 2012.08.30
申请号 JP20110026013 申请日期 2011.02.09
申请人 MEGA CHIPS CORP 发明人 CHIN KANTATSU
分类号 H04J11/00;H04L7/00 主分类号 H04J11/00
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