CAPACITANCE DETECTION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten a data update rate without deteriorating precision (quantization noise) of a delta sigma AD converter in a capacitance detection circuit.

SOLUTION: The frequency of a sampling clock ADC_CLK of a delta sigma AD converter 16 is set to be higher than the frequency of an amplifier clock AMP_CLK of a charge amplifier 14 so as to shorten the data update rate of N-bit digital data AD_OUT output from the delta sigma AD converter 16. Further, a track holding circuit 15 is interposed between the charge amplifier 14 and delta sigma AD converter 16 so as to periodically take in and hold only an output voltage AMP_OUT in a charge transfer mode of the charge amplifier 14.

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