| 摘要 |
PURPOSE: A gate driving circuit is provided to prevent a leakage current through switching elements by forming a low voltage of an output control clock pulse lower than a low voltage of an output clock pulse. CONSTITUTION: The 1/3 portion of high durations of a first to a fourth output clock pulses are overlapped. The first to the fourth output clock pulses includes a plurality of impulses periodically generated. A rising edge of the first output clock pulse is located on the high duration of a first output control clock pulse. A rising edge of the second output clock pulse is located on the high duration of a second output control clock pulse. A rising edge of the third output clock pulse is located on the high duration of a third output control clock pulse. A rising edge of the fourth output clock pulse is located on the high duration of a fourth output control clock pulse.
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