发明名称 |
DELAY CELL FOR CLOCK SIGNALS |
摘要 |
An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations |
申请公布号 |
WO2012115880(A1) |
申请公布日期 |
2012.08.30 |
申请号 |
WO2012US25695 |
申请日期 |
2012.02.17 |
申请人 |
QUALCOM INCORPORATED;QUAN, XIAOHONG;SRIVASTAVA, ANKIT |
发明人 |
QUAN, XIAOHONG;SRIVASTAVA, ANKIT |
分类号 |
H03K5/13 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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