发明名称 REDUCED LATENCY BARRIER TRANSACTION REQUESTS IN INTERCONNECTS
摘要 Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
申请公布号 KR20120095876(A) 申请公布日期 2012.08.29
申请号 KR20127010025 申请日期 2010.09.28
申请人 ARM LIMITED 发明人 RIOCREUX PETER ANDREW;MATHEWSON BRUCE JAMES;LAYCOCK CHRISTOPHER WILLIAM;GRISENTHWAITE RICHARD ROY
分类号 G06F13/14 主分类号 G06F13/14
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