| 摘要 |
The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of a second port, respectively. When the mode change signal is H level, the EEPROM is set to a combine mode. In this case, the first and second memory banks are combined into a 4k-bit memory bank, and accessed by the control signal of the first port. |
