发明名称 |
Method for fabricating CMOS transistor |
摘要 |
A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer. |
申请公布号 |
US8252650(B1) |
申请公布日期 |
2012.08.28 |
申请号 |
US201113092151 |
申请日期 |
2011.04.22 |
申请人 |
CHANG FENG-YI;LIN YI-PO;LIAO JIUNN-HSIUNG;TSAI SHANG-YUAN;FENG CHIH-WEN;LU SHUI-YEN;HSU CHING-PIN;UNITED MICROELECTRONICS CORP. |
发明人 |
CHANG FENG-YI;LIN YI-PO;LIAO JIUNN-HSIUNG;TSAI SHANG-YUAN;FENG CHIH-WEN;LU SHUI-YEN;HSU CHING-PIN |
分类号 |
H01L21/8234 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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