发明名称 SERIAL INTERFACE
摘要 <p>A serial interface comprises a clock line, a request line, a ready line, a master-to- slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.</p>
申请公布号 WO2012110798(A1) 申请公布日期 2012.08.23
申请号 WO2012GB50324 申请日期 2012.02.14
申请人 NORDIC SEMICONDUCTOR ASA;CHETTIMADA, VINAYAK KARIAPPA;TARALDSEN, BJOERN TORE;SKOGLUND, PER CARSTEN;WILSON, TIMOTHY JAMES 发明人 CHETTIMADA, VINAYAK KARIAPPA;TARALDSEN, BJOERN TORE;SKOGLUND, PER CARSTEN
分类号 G06F13/42 主分类号 G06F13/42
代理机构 代理人
主权项
地址