发明名称 INTEGRATED CIRCUIT WITH TAMPER-DETECTION AND SELF-ERASE MECHANISMS
摘要 Methods and apparatuses for improving security of an integrated circuit (IC) are provided. A tamper condition is detected and a digital key stored in the IC is erased. The digital key is associated with a first image loaded onto the IC from a first memory. The memory may be a non-volatile memory module. A second image is loaded into a second memory module. The second memory module may be an embedded memory module, e.g., a control random access memory (CRAM) module. The first image is then erased from the first and second memory modules.
申请公布号 US2012216001(A1) 申请公布日期 2012.08.23
申请号 US201113031804 申请日期 2011.02.22
申请人 发明人 RAMLY NOOR HAZLINA;YAP YIN MEI
分类号 G06F12/14 主分类号 G06F12/14
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