发明名称 Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the Method
摘要 A method for fabricating an integrated circuit chip-scale package and a device made from the method. One or more IC chips are mounted on a carrier and a stud bump defined on an IC pad. The stud-bumped IC is encapsulated to define a potted assembly layer which is thinned to expose the stud bump. Conductive first traces are defined and coupled to the stud bump to reroute the IC pads. A dielectric layer is provided and vias defined there through to expose the first traces. Electrically conductive second traces are disposed on the dielectric layer surface that are coupled to the first traces to reroute the IC pads to define a chip scale package.
申请公布号 US2012211886(A1) 申请公布日期 2012.08.23
申请号 US201213399051 申请日期 2012.02.17
申请人 LIEU PETER;YAMAGUCHI JAMES;BINDRUP RANDY;BOYD W. ERIC;ISC8 INC. 发明人 LIEU PETER;YAMAGUCHI JAMES;BINDRUP RANDY;BOYD W. ERIC
分类号 H01L23/498;H01L21/50 主分类号 H01L23/498
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