发明名称 |
Mode Latching Buffer Circuit |
摘要 |
A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply. |
申请公布号 |
US2012212256(A1) |
申请公布日期 |
2012.08.23 |
申请号 |
US201113031176 |
申请日期 |
2011.02.18 |
申请人 |
NICHOLAS PETER J.;KRIZ JOHN CHRISTOPHER;BHATTACHARYA DIPANKAR;BRADLEY JAMES JOHN;LSI CORPORATION |
发明人 |
NICHOLAS PETER J.;KRIZ JOHN CHRISTOPHER;BHATTACHARYA DIPANKAR;BRADLEY JAMES JOHN |
分类号 |
H03K19/0175;H03K5/08 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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