发明名称 CLOCK BUFFER CIRCUIT AND CLOCK DISTRIBUTION CIRCUIT USING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock buffer circuit that is compliant with a wideband of clock signals in a small circuit scale. <P>SOLUTION: A clock buffer circuit 100 of an embodiment includes a driver section 11 and an LC tank section 21. The driver section 11 outputs at least non-inverted outputs of input clock signals from clock inputs IN, INB to clock outputs OUT, OUTB, respectively. The LC tank section is disposed between the driver section 11 and the clock outputs OUT, OUTB. The driver section 11 has switches SW1, SW2 for short-circuiting the inputs and outputs of the driver section 11 in response to control signals corresponding to frequencies of the input clock signals. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012161039(A) 申请公布日期 2012.08.23
申请号 JP20110021050 申请日期 2011.02.02
申请人 RENESAS ELECTRONICS CORP 发明人 TANABE AKIRA
分类号 H03K5/151;H03K19/0175 主分类号 H03K5/151
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