| 摘要 |
A method of generating a hardware design for a pipelined parallel stream processor, suitable for implementation on a Field Programmable Gate Array (FPGA), includes: defining 302 a processing operation to be implemented in hardware; defining 304 a graph representing the processing operation, the graph including at least one data path configured to enable data to be streamed therethrough and at least one object corresponding to a hardware element of the processor, the object being operable to execute a function having an associated latency; defining 308 the data path and associated latencies as a set of algebraic linear inequalities; solving 310 the set of linear inequalities; optimising 312, 314 the data path to produce an optimised graph; and using the optimised graph to define 316, 318 the optimised hardware design. Optimising the graph may include optimising (minimising) the buffering required to schedule the data path. In other embodiments, the optimisation may include providing a stream offset object in the data path, the stream offset being operable to access data from a previous clock cycle and being equivalent to an identity node with negative latency. The invention may also handle loops.
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