发明名称 Debug architecture
摘要 Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit; a shared hub; and between each respective debug unit and the shared hub, a single physical interface configured to transport both configuration data and event data, wherein the interface is configured such that if an event occurs whilst the interface is transporting configuration data, the interface interrupts the transport of the configuration data in order to transport the event data.
申请公布号 GB201212177(D0) 申请公布日期 2012.08.22
申请号 GB20120012177 申请日期 2012.07.09
申请人 ULTRASOC TECHNOLOGIES LTD 发明人
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