发明名称 |
HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES |
摘要 |
<p>Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.</p> |
申请公布号 |
EP2489127(A2) |
申请公布日期 |
2012.08.22 |
申请号 |
EP20100824014 |
申请日期 |
2010.10.13 |
申请人 |
CHAOLOGIX, INC. |
发明人 |
MYERS, BRENT, A.;FOX, JAMES, G. |
分类号 |
H03K19/173;G06F21/55;H03K19/00;H03K19/0944;H03K19/177;H03K19/20;H04L9/00 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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