发明名称 Memory system with potential rank correction capability
摘要 A memory system includes a cell array including a plurality of nonvolatile memory cells electrically connected to a common word line, each memory cell storing a plurality of bits including a plurality of potential ranks, and a controller measuring a potential of the memory cell for each potential rank and changing a lower limit and upper limit of the potential rank based on the measurement result.
申请公布号 US8248857(B2) 申请公布日期 2012.08.21
申请号 US20090644685 申请日期 2009.12.22
申请人 TANAKA HIROAKI;MURAKAMI TETSUYA;KABUSHIKI KAISHA TOSHIBA 发明人 TANAKA HIROAKI;MURAKAMI TETSUYA
分类号 G11C11/34;G11C16/04 主分类号 G11C11/34
代理机构 代理人
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