发明名称 |
Compiling code for parallel processing architectures based on control flow |
摘要 |
A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; for each of a first subset of branches in the control flow graph, scheduling a value of an associated branch condition to be broadcast to multiple computation units; for each of a second subset of branches in the control flow graph, representing each instruction dependent on an associated branch condition as a predicated instruction that includes a predicate for computing the associated branch condition; assigning each subset of instructions to one of the computation units for execution on the assigned computation unit; and converting at least some of the predicated instructions in a subset of instructions assigned to a given computation unit into unpredicated instructions that depend on a branch local to the given computation unit.
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申请公布号 |
US8250555(B1) |
申请公布日期 |
2012.08.21 |
申请号 |
US20080028002 |
申请日期 |
2008.02.07 |
申请人 |
LEE WALTER;GOTTLIEB ROBERT A.;SONI VINEET;AGARWAL ANANT;SCHOOLER RICHARD;TILERA CORPORATION |
发明人 |
LEE WALTER;GOTTLIEB ROBERT A.;SONI VINEET;AGARWAL ANANT;SCHOOLER RICHARD |
分类号 |
G06F9/44;G06F9/45 |
主分类号 |
G06F9/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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