发明名称 |
Partitioned replacement for cache memory |
摘要 |
In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event. |
申请公布号 |
US8250332(B2) |
申请公布日期 |
2012.08.21 |
申请号 |
US20090482529 |
申请日期 |
2009.06.11 |
申请人 |
PLONDKE ERICH JAMES;CODRESCU LUCIAN;INGLE AJAY;QUALCOMM INCORPORATED |
发明人 |
PLONDKE ERICH JAMES;CODRESCU LUCIAN;INGLE AJAY |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|