| 摘要 |
An endoscope signal processor to which an endoscope having an image pickup device is detachably connected has a phase-locked loop circuit in which a phase comparator compares a phase of a variable clock with that of a reference clock output from the image pickup device to generate a variable clock phase-synchronized with the reference clock. The processor includes a gate section opened or closed to input of the reference clock to the phase comparator, an operation control signal generation section which generates an operation control signal for setting the phase-locked loop circuit in a closed loop operable state during intermittent periods, and a sync timing setting section which synchronizes a timing of starting the generation of the operation control signal with a timing of input of the variable clock to the phase comparator at least within a predetermined time period shorter than the cycle of the variable clock. |
