发明名称 |
Digital phase lock system with dithering pulse-width-modulation controller |
摘要 |
A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths. |
申请公布号 |
US8248127(B2) |
申请公布日期 |
2012.08.21 |
申请号 |
US20100851209 |
申请日期 |
2010.08.05 |
申请人 |
CHAN CHI FAT;LIN CHIEN-WEI;CHUNG GORDON;HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCHINSTITUTE CO., LTD. |
发明人 |
CHAN CHI FAT;LIN CHIEN-WEI;CHUNG GORDON |
分类号 |
H03K3/017;H03K5/04;H03K7/08 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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