发明名称 |
High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider |
摘要 |
A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. |
申请公布号 |
US8248118(B2) |
申请公布日期 |
2012.08.21 |
申请号 |
US20100852520 |
申请日期 |
2010.08.09 |
申请人 |
SUBBURAJ KARTHIK;K DHANYA;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SUBBURAJ KARTHIK;K DHANYA |
分类号 |
H03K21/00;H03K23/00;H03K25/00 |
主分类号 |
H03K21/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|