发明名称 |
METHOD FOR MODELING OF CHARGE TRAPPING AND RELEASE INDUCED THRESHOLD VOLTAGE SHIFT IN THIN FILM TRANSISTOR |
摘要 |
<p>PURPOSE: A method for modeling a threshold voltage shift by trapping and discharging charges in a thin film transistor is provided to improve the reliability of an operation simulation result of a circuit by estimating the threshold voltage shift of a transistor based on the trap and discharge of a charge carrier. CONSTITUTION: An interface on a semiconductor and a dielectric interface are displayed(112). A localized state or trap state on a dielectric layer is displayed(113). An interface on the semiconductor and a protection interface are displayed(114). A localized state or trap state on a protection layer is displayed(115). A conduction band is displayed to show an electron transfer band(131). A gate electrode state is displayed(135).</p> |
申请公布号 |
KR101175199(B1) |
申请公布日期 |
2012.08.20 |
申请号 |
KR20120068724 |
申请日期 |
2012.06.26 |
申请人 |
SEOUL NATIONAL UNIVERSITY OF TECHNOLOGY CENTER FOR INDUSTRY COLLABORATION |
发明人 |
JUNG, TAE HO |
分类号 |
H01L29/786 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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