发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME |
摘要 |
<p>PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to reduce parasitic capacitance between adjacent bit lines by differently forming the depth of an adjacent bit line. CONSTITUTION: A bit line(102b) is formed on a first insulator(101). A second insulator(103) and a third insulator(104) are formed on the bit line. A first contact plug(105a,105b) is connected to the bit line. A conductive layer(107) is formed on a fourth insulator(106). A groove is formed by etching the conductive layer and the fourth insulator.</p> |
申请公布号 |
KR20120090836(A) |
申请公布日期 |
2012.08.17 |
申请号 |
KR20120011599 |
申请日期 |
2012.02.06 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
TAKEMURA YASUHIKO |
分类号 |
H01L27/108;H01L21/8242 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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