发明名称 VECTOR CONFLICT INSTRUCTIONS
摘要 A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
申请公布号 WO2012087548(A3) 申请公布日期 2012.08.16
申请号 WO2011US63307 申请日期 2011.12.05
申请人 INTEL CORPORATION;HUGHES, CHRISTOPHER J.;CHARNEY, MARK J.;CHEN, YEN-KUANG;CORBAL, JESUS;FORSYTH, ANDREW T.;GIRKAR, MILIND B.;HALL, JONATHAN C.;IDO, HIDEKI;VALENTINE, ROBERT;WIEDEMEIER, JEFFREY 发明人 HUGHES, CHRISTOPHER J.;CHARNEY, MARK J.;CHEN, YEN-KUANG;CORBAL, JESUS;FORSYTH, ANDREW T.;GIRKAR, MILIND B.;HALL, JONATHAN C.;IDO, HIDEKI;VALENTINE, ROBERT;WIEDEMEIER, JEFFREY
分类号 G06F9/30 主分类号 G06F9/30
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