| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide ASIC equivalents of FPGAs more efficiently and economically. <P>SOLUTION: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (HLEs), each of which can provide a portion of the full functionality of an FPGA logic element (LE). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without resynthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without resynthesis) in either direction between FPGA and ASIC designs. <P>COPYRIGHT: (C)2012,JPO&INPIT |
