发明名称 PACKAGING CONFIGURATIONS FOR VERTICAL ELECTRONIC DEVICES USING CONDUCTIVE TRACES DISPOSED ON LAMINATED BOARD LAYERS
摘要 This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.
申请公布号 US2012205803(A1) 申请公布日期 2012.08.16
申请号 US201213454342 申请日期 2012.04.24
申请人 发明人 SUN MING;HO YUEH SE
分类号 H01L23/485;H01L21/60 主分类号 H01L23/485
代理机构 代理人
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