| 摘要 |
<P>PROBLEM TO BE SOLVED: To allow an original serial data signal to be correctly received based on a parallel data signal and a recovery clock signal outputted from SERDES in the case where the SERDES receives the serial data signal containing jitter by oversampling operation. <P>SOLUTION: A semiconductor integrated circuit device includes a clock data recovery circuit which generates a second parallel data signal of KN/m bit (N/m is even number) based on a first parallel data signal of N bit outputted from an SERDES circuit that oversamples a serial data signal by m times (m is exponentiation of 2), and generates a second recovery clock signal by applying K-frequency division (K is exponentiation of 2) to a first recovery clock signal outputted from the SERDES circuit, for synchronizing the second parallel data signal with the second recovery clock signal and outputting. <P>COPYRIGHT: (C)2012,JPO&INPIT |
