| 摘要 |
A computer-readable medium stores therein a verification support program that causes a computer to execute a process including first detecting an assertion that evaluates to true during simulation of a circuit, the assertion being detected from an assertion group prescribing values of registers to be met by the circuit; updating, at a clock tick subsequent to a clock tick at which the assertion is detected at the first detecting, an expected value of a register, to a value of the register as prescribed by the assertion; second detecting inconsistency between the expected value that has been updated at the updating and the value of the register; determining, based on a detection result obtained at the second detecting, validity of a change in the value of the register; and outputting a determination result obtained at the determining. |
