发明名称 |
Semiconductor integrated circuit test method |
摘要 |
A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly. |
申请公布号 |
US8241926(B2) |
申请公布日期 |
2012.08.14 |
申请号 |
US20100710377 |
申请日期 |
2010.02.23 |
申请人 |
YOSHIKAWA YASUHIRO;OKI SEMICONDUCTOR CO., LTD. |
发明人 |
YOSHIKAWA YASUHIRO |
分类号 |
G01R31/26;G01R31/00;G01R31/02;H01L21/66 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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