发明名称 Multi-bit memory error management
摘要 Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
申请公布号 US8245087(B2) 申请公布日期 2012.08.14
申请号 US20070693572 申请日期 2007.03.29
申请人 ABTS DENNIS C.;HIGGINS MICHAEL;SNYDER VAN L.;CRAY INC. 发明人 ABTS DENNIS C.;HIGGINS MICHAEL;SNYDER VAN L.
分类号 G06F11/00 主分类号 G06F11/00
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