| 摘要 |
There is provided with simulation execution apparatus including: a receiving unit configured to receive a cyclic signal; registers; a simulation execution unit configured to execute simulation of a logic circuit model which operates with the use of the cyclic signal and the registers; a counter configured to count time based on the cyclic signal; a register value monitoring unit configured to monitor the values of the registers; a register data recording unit configured to record in a storage, register data made up of the values of the registers in association with the time of the counter when the value of at least one of the registers is changed; a cyclicity detection unit configured to detect a cyclicity of the register data based on the storage; and a stop unit configured to give a stop instruction signal which instructs stop of the simulation execution to the simulation execution unit. |
