| 摘要 |
A shaper of single packets of pulses with programmable pulse width and pause, number of pulses in a packet, and delay thereof relative to the start pulse contains two reversible binary countdown counters, each of which has a sync input, a synchronous parallel load input and data loading inputs, a counter mode enable input, an asynchronous reset, an overflow output, an element OR, an inverter, a circuit comprising in series connected resistor and capacitor, a start-stop device comprising a synchronous D-flip-flop with asynchronous reset, first and second two-input AND elements. A work memory made in the form of a circuit of register file with independent writing and reading, which has a data bus forming inputs of shaper programming on set time parameters of pulses in the packet, an address write bus, a write enable input, an address read bus, a read enable input, an asynchronous reset are introduced. |
