| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an SOI-MISFET which inhibits electrical short circuit due to residual of polycrystalline silicon, increase of parasitic capacitance in a gate electrode and a reverse narrow channel effect. <P>SOLUTION: A gate insulation film 14, a first polycrystalline silicon film 15 and a stopper nitride film 16 are sequentially deposited on an SOI substrate having a silicon film 13. Etching is performed so as to form reverse tapered surfaces (taper angle θ is obtuse angle) on side faces of the silicon film 13 and the polycrystalline silicon film 15 to form an element isolation trench. After an STI implanted insulation film 17 is deposited and planarized by CMP, a flat surface is obtained by etching of the stopper nitride film 16 and the insulation film 17 by constant velocity RIE, and a second polycrystalline silicon film 18 is deposited on the flat surface (e). Laminated gate electrodes (15, 18) are formed by etching of a laminated polycrystalline silicon film (f). Subsequently, a source/drain region 21, a silicide film 22, an interlayer insulation film 23, metal wiring 24 and the like are formed (g). <P>COPYRIGHT: (C)2012,JPO&INPIT |
