发明名称 |
Method and Transceiver System Having a Transmit Clock Signal Phase that is Phase-Locked with a Receive Clock Signal Phase |
摘要 |
A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed. |
申请公布号 |
US2012201280(A1) |
申请公布日期 |
2012.08.09 |
申请号 |
US201213367282 |
申请日期 |
2012.02.06 |
申请人 |
AMIRICHIMEH ABBAS;BAUMER HOWARD;LOUIE JOHN;PARTHASARATHY VASUDEVAN;YING LINDA;BROADCOM CORPORATION |
发明人 |
AMIRICHIMEH ABBAS;BAUMER HOWARD;LOUIE JOHN;PARTHASARATHY VASUDEVAN;YING LINDA |
分类号 |
H04B1/38;H03K5/135;H04L7/00 |
主分类号 |
H04B1/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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