发明名称 |
PHASE-LOCK ASSISTANT CIRCUITRY |
摘要 |
A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
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申请公布号 |
US2012200323(A1) |
申请公布日期 |
2012.08.09 |
申请号 |
US201213448878 |
申请日期 |
2012.04.17 |
申请人 |
LIN CHIH-CHANG;CHERN CHAN-HONG;SWEI STEVEN;HUANG MING-CHIEH;YANG TIEN-CHUN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIN CHIH-CHANG;CHERN CHAN-HONG;SWEI STEVEN;HUANG MING-CHIEH;YANG TIEN-CHUN |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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