| 摘要 |
A graphic processor device is implemented on a field programmable gate array ("FPGA") circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution. |
