| 摘要 |
<P>PROBLEM TO BE SOLVED: To realize a vertical binning operation by a small vertical shift register. <P>SOLUTION: Vertical shift register parts 40a and 40b include M pieces of logic circuits LO<SB POS="POST">1</SB>to LO<SB POS="POST">M</SB>which output a row selecting control signal to each of M pieces of row selecting wirings L<SB POS="POST">V,1</SB>to L<SB POS="POST">V,M</SB>, and a shift register circuit 43 arranged for each of the two row selecting wirings L<SB POS="POST">V</SB>. The M pieces of logic circuits LO<SB POS="POST">1</SB>to LO<SB POS="POST">M</SB>output a row selecting control signal Vsel so as to close a reading switch SW<SB POS="POST">1</SB>when a binning control signal Vbin<SB POS="POST">1</SB>or Vbin<SB POS="POST">2</SB>and an output signal of the shift register circuit 43 are both significant values. The vertical shift register parts 40a and 40b realize a normal operation mode for sequentially selecting the two row selecting wirings L<SB POS="POST">V</SB>and a binning operation mode for simultaneously selecting the two row selecting wirings L<SB POS="POST">V</SB>, by controlling such timing as the binning control signals Vbin<SB POS="POST">1</SB>and Vbin<SB POS="POST">2</SB>come to be significant values. <P>COPYRIGHT: (C)2012,JPO&INPIT |
